To reduce the impact of Programmed I/O (PIO) write latency in PCI express (PCIe) transmission process, too many times of interaction between the host and the embedded processing system and other issues on transmission bandwidth, a Direct Memory Access (DMA) controller based on command buffering mechanism was designed to improve the transmission bandwidth utilization. Using the internal command buffer of the Field-Programmable Gate Array (FPGA), the DMA controller could cache the data transfer request of the PC. The FPGA could dynamically access the storage space of the PC according to its own requirements and enhance the transmission flexibility. At the same time, a dynamic mosaic DMA scheduling method was proposed to reduce the times of host-to-hardware interaction and interrupt generation by merging the access requests of adjacent storage areas. In the system transmission rate test, the maximum write speed of DMA was 1631 MB/s, the maximum rate of DMA read was up to 1582 MB/s, the maximum of bandwidth was up to 85.4% of the theoretical bandwidth of PCIe bus. Compared with the traditional PIO mode DMA transfer method, DMA read bandwidth increased by 58%, DMA write bandwidth increased by 36%. The experimental results show that the proposed design can effectively improve the DMA transfer efficiency, and is significantly better than PIO method.